There have been found to be advantages to combining CMOS and bipolar circuits on the same integrated circuit. Such integrated circuits are commonly known as BICMOS. The advantage of CMOS is generally recognized as providing low power consumption, particularly for the case where the circuit has completed switching. Bipolar has the advantage of speed and power. Typically, in implementing a function, the CMOS performs the logic and the bipolar provides the drive. The actual drive circuit may include some MOS transistors in addition to the bipolar transistors. In the case of a NAND gate, for example, the typical implementation is to have the input signals received by a conventional CMOS configuration. The CMOS configuration performs the logic and provides and output which is then driven by a circuit which includes bipolar transistors. This type of approach, for example, is shown in U.S. Pat. Nos. 4,733,110 and 4,752,982, both Hara et al. U.S. Pat. Nos. 4,716,310, Tanizawa et al, 4,701,642, Pricer, and 4,694,203, Uragami et al, are other examples of CMOS logic followed by drivers which include bipolar transistors.
Another BICMOS circuit that has been found to be advantageous is a P channel transistor and an NPN transistor in which the drain of the P channel transistor drives into the base of the NPN transistor. This results in particularly good performance. This has been described in U.S. Pat. No. 4,694,202, Iwamura et al. One way this has been implemented is as an inverter in which the emitter provides the output of the inverter. In such a case a resistor is used in conjunction with the P channel transistor and the NPN transistor. This resistor is connected to the base of the bipolar transistor and the output of the inverter. An N channel transistor is connected to the output of the inverter to act as the pull-down device of the inverter. It is normal for an N channel transistor to act as a pull-down device. This has the effect of placing the resistor in series between the P channel transistor and the N channel pull-down transistor.
This P channel and NPN combination was also used to make a NAND gates. Two configurations of NAND gates using this combination were disclosed in the '202 patent. One was shown in FIG. 14 and the other in FIG. 15. The resulting configurations had the P channel transistors all connected to the same node which is consistent with common approach of using the CMOS for the logic function and driving the output of the CMOS circuit with bipolar devices. This has a deleterious effect on the speed. The intent of the combination was to make the circuit operate faster. The creation of the NAND gate function created a high capacitance node which was driven only by P channel transistors, the transistor type of those present which is least able to quickly drive a node. The increased capacitance of the node driven exclusively by P channel transistors is increased even more as the number of inputs is increased. The number of inputs can be quite substantial. The desired use of the NAND gate might be, for example, a decoding function in a memory where the inputs could be desirably quite large.